1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a data writing method for controlling a biasing level of a memory cell array.
2. Discussion of the Related Art
Phase change random access memories (PRAMs) are nonvolatile memory devices which store data using a phase change material, e.g., Ge—Sb—Te (GST), whose resistance changes in accordance with a phase transition due to a change in temperature.
FIG. 1 illustrates an equivalent circuit of a unit cell C of a PRAM. Referring to FIG. 1, the unit cell C consists of a P—N diode D and a phase change material GST. The phase change material GST is connected to a bit line BL and a P-junction of the diode D. A word line WL is connected to an N-junction of the diode D.
The phase change material GST of the PRAM unit cell C, goes into a crystalline state or an amorphous state depending on a temperature applied thereto and a heating time. This enables data to be stored in the PRAM cell. In general, a temperature higher than 900° C. is needed for a phase transition of the phase change material GST. Such temperatures are obtained by Joule heating which uses a current flowing through the PRAM cell to increase or decrease the temperature thereof.
A write operation for the phase change material GST will now be described. First, the phase change material GST is heated above its melting temperature by a current and then it is rapidly cooled. The phase change material GST then goes into the amorphous state and stores a data “1”. This state is referred to as a reset state. The phase change material GST is then heated above its crystallization temperature for a predetermined period of time and cooled. Next, the phase change material GST goes into the crystalline state and stores a data “0”. This state is referred to as a set state.
A read operation for the phase change material GST will now be described. After a bit line and a word line are used to select a memory cell, an external current is provided to the selected memory cell. It is then determined whether data to be stored in the selected memory cell is “1” or “0” based on a change in voltage according to a resistance value of the phase change material GST of the selected memory cell.
FIG. 2 illustrates a semiconductor memory device 200 comprising a memory cell array MAY including a plurality of the PRAM unit cells C shown in FIG. 1. An exemplary structure of the memory cell array MAY is disclosed in U.S. Pat. Nos. 6,667,900 and 6,567,296.
Referring to FIG. 2, the semiconductor memory device 200 comprises the memory cell array MAY and a word line driver 210. The memory cell array MAY comprises a plurality of unit cells C connected to corresponding bit lines BL0˜BLk-1 and word lines WL0, WL1, and WL2. Although only k bit lines BL0˜BLk-1 and three word lines WL0, WL1, and WL2 are shown in FIG. 2, the number of bit lines and word lines is not limited thereto.
For a data write operation, if one of the bit lines BL0˜BLk-1 is first selected, the word line driver 210 selects one of the word lines WL0, WL1, and WL2. The selected word line is then set to a low level. If a first bit line BL0 and a first word line WL0 are sequentially selected, a write current applied to the first bit line BL0 flows through a unit cell connected between the first bit line BL0 and the first word line WL0. The state of the phase change material of the unit cell is then changed to store data.
Each of the word lines WL0, WL1, and WL2 has its own resistance R_WL. Since the word lines WL0, WL1, and WL2 pass current when writing data, the resistance R_WL should be minimized. However, since the word lines WL0, WL1, and WL2 have a high resistance, the number of unit cells connected to the word lines WL0, WL1, and WL2 is limited. Further, the word line driver 210 should be powerful enough to drive the word lines WL0, WL1, and WL2.
When data is written to the unit cell connected between the first bit line BL0 and the first word line WL0, the write current is applied to the first bit line BL0, and the first word line WL0 is set to a low level by the word line driver 210. The second and third word lines WL1 and WL2 are then in a floating state. The first bit line BL0 maintains a relatively high voltage due to the applied write current, and the second and third word lines WL1 and WL2 maintain a relatively low level in the floating state. Therefore, current flows through unit cells connected between the first word line WL0 and the second and third word lines WL1 and WL2, which can change the state of the phase change material in those unit cells.
Since current may flow through unselected word lines that are floating, it is difficult to increase the operating speed of the semiconductor memory device and perform stable sensing. As such, a need exists for a semiconductor memory device that is capable of performing a stable sensing operation while increasing its operating speed.